For example, JP-A 2009-146954 proposes a technique to arrange memory cells in a three-dimensional array by forming memory holes in a stacked body having multiple conductive layers and insulating layers alternately stacked therein, the conductive layers serving as control gates in a memory device, and by providing silicon in the memory holes after forming charge storage films on inner walls of the memory holes.
Also, JP-A 2009-146954 discloses the processing of an end portion on a peripheral region side of the stacked body into a staircase pattern by repeating slimming of a resist film and reactive ion etching (RIE) on the stacked body using the resist film as a mask. However, in such a processing method, the resist film is retreated in a width direction and in a film thickness direction during slimming of the resist film. As a result, particularly when the number of layers in the stacked body is increased, there is a risk that the resist film is retreated in thickness, and eventually is completely removed.